Registered Strategy B on the T-S01 profile

This is one exploratory measurement of the integrated public StrategyPort path using registered HiGHS LP and convex providers. It is not a strategy comparison, speedup, application-scale result, or scalability claim.

Algorithm source commit: 2a5ab835295dfd22f02b19d440bb8158267d985a; harness: 4fc8e28587a7fe0e4130f1cb435cf6502ba0e4e2. Profile: ts01_exact_integrator. Assumptions:

• Discrete two-step scalar integrator at times 0, 1, 2.
• Known initial state x0=0; all state constraints are universal.
• Both transitions are x[t+1]=x[t]+u[t] with zero affine offsets and no external channels.
• Continuous controls independently constrained to [0,1].
• Nominal open-loop information; no observations or temporal constraints.
• Terminal quadratic objective J(x2)=x2^2-2*x2+1=(x2-1)^2.
• Effective request asks for exact_optimal_relation in H-representation under Assurance::numerical and no materialization limit.

Analytic T-S01 relation

For x₀=0, xₜ₊₁=xₜ+uₜ, u₀,u₁∈[0,1] and J(x₂)=(x₂−1)², the complete relation is (x₀,x₁,x₂,u₀,u₁)=(0,s,1,s,1−s), 0≤s≤1. Each timed run required a registry-verified complete-family result and checked the literal canonical H-representation and exact membership/nonmembership points.

Completeness is limited to this exact admitted T-S01 profile under its declared Assurance::numerical evidence path. Each output names the accepted compiled verifier csl.verifier.ts01-analytic@1; no generic strategy coverage or validated-arithmetic assurance is implied.

Each result also retained one independently checked optimizer anchor with original objective 0. The reported maximum trajectory residuals are 0–0 under absolute and relative tolerances 1e−8; the exact verifier ID is in each raw event.

Observed timings

Fresh problem construction and resolution, registered Strategy B and HiGHS LP/convex provider creation/selection, StrategyRegistry preparation, exclusive public StrategyPort workspace creation and run, compiled T-S01 verifier acceptance, and exact canonical H-relation plus exact-membership validation. Excludes process startup, JSON serialization, build, file persistence, and rendering.

One excluded warmup; seven measured runs. Median 982800 ns; range 962500–1087100 ns (width 124600 ns). Failures: 0.

Performance conclusion: inconclusive. Windows Performance Recorder was denied by policy (0xc5585011), while Visual Studio process-scoped CPU Usage sampling succeeded without SeSystemProfilePrivilege. A separate 20-process sequential PDB-enabled Release diagnostic profile (1,337 target stack samples; zero lost ETW events) resolves a sampled path through StrategyPort, DirectJointWorkspace, and the HiGHS QP solver. This identifies an observed CPU stack hotspot, not a proven limiter on unprofiled single-process latency; profiling runs are excluded from reported timings. See profile commands and detailed evidence.

Evidence limits

• Complete-family verification applies only to the exact admitted T-S01 profile and registered csl.verifier.ts01-analytic v1.
• The result reports Assurance::numerical; validated arithmetic assurance is unavailable.
• This is one Strategy B measurement, not a comparison, speedup, application-scale, throughput, or scalability claim.
• All seven trials are tiny analytic T-S01 fixtures; no general performance inference follows.
• WPR CPU stack collection was denied by Windows policy, but Visual Studio process-scoped CPU Usage sampling succeeded without SeSystemProfilePrivilege.
• A separate 20-process sequential PDB-enabled Release diagnostic profile resolved a sampled CPU path through StrategyPort, DirectJointWorkspace, and the HiGHS QP solver; this does not establish an unprofiled latency limiter.
• The diagnostic profile is separate and excluded from all reported latency statistics; profiling overhead and build symbols may affect sampling.
• Internal preparation, LP, QP, extraction, verifier and export timing counters are unavailable.

Environment and reproduction evidence

Machine, operating system, compiler, Release configuration, dependency pins, provider identity, system load observations, profiling attempt and all unavailable phase counters are retained in the machine-readable sidecars.

Typed report · Raw timing events · Timing CSV · Measurement and host evidence · Build provenance · Scenario · WPR profile attempt · Visual Studio CPU sample profile

This result is partial SYN-04 evidence and does not close issue #67.

Publication syn04-strategy-b-ts01-46513fc77b3e1e9e7795b887b1d2a12d7bfa5dbde4d6c74563b7f06c6a0aff24; source report syn04-strategy-b-ts01-20261014-2a5ab835. Versioned envelope · Publication manifest